1. Field of the Invention
The present invention relates to a successive approximation analog-to-digital (a-d) converter, and more specifically to such a kind of monolithic type of a-d converter including an improved digital-to-analog (d-a) converter, which a-d converter is manufactured by C-MOS (Complementary-Metal-Oxide-Semiconductor) techniques.
2. Description of the Prior Art
Various attempts have been made to develop a-d converters using MOS techniques. One of such a-d converter is disclosed in U.S. Pat. No. 4,293,848 (corresponding to Japanese Patent Application No. 54-46461).
This prior art teaches an a-d converter operable with a single power supply and featuring conversion of an analog input signal up to a potential equal to that of the power supply using only one bootstrap circuit. This prior art however encounters the drawbacks that: (a) voltage dividing errors tend to occur which increase gain errors, since an analog input signal is capacitively voltage divided into two, and since one half of a reference voltage (Vref) is obtained by a resistor-ladder network including a considerable number of resistors (2.times.2.sup.N) (wherein "N" denotes the bits of a digital output), and (b) the large number of resistors used occupies an undesirable amount of chip area inducing increased manufacturing cost.
Another 8-bit a-d converter using C-MOS techniques is disclosed on pages 131-135 of "Electronics" (Apr. 27, 1978). This second prior art arrangement includes a d-a converter including 256 (viz., 2.sup.8) resistors connected in series and 510 switches for deriving voltages at the nodes of these resistors. This second prior art is similarly plagued by the large number of resistors as well as switches. In general this type of N-bit a-d converters, require 2.sup.N resistors and (2.sup.N+1 -1) switches, and hence consume a large amount of chip space, induce high manufacturing cost, and low production rate due to the large number of circuit elements. Further, these arrangements encounter the problem that the conversion speed is limited due to on-resistance of N switches coupled in series between each resistor node and a comparator.